M5 Bugs

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FS#270 — cache and bus reschedule on next tick instead of next clock

Attached to Project— M5 Bugs
Opened by Steve Reinhardt (stever) - Wednesday, 16 May 2007, 05:55PM
Last edited by Ali Saidi (saidi) - Friday, 11 April 2008, 02:07PM
Bug
Memory System
New
No-one
All
Medium
Normal
2.0beta2
2.0
Undecided
0%
Lots of "retry" type events get scheduled at curTick+1 when they really should be scheduled for the next device clock edge (if not later). Requires adding the notion of a clock to the cache. Depends on new mechanism to be added for having per-object clocks.