FS#261 — Make bus bridge use 1 line cache for partial block writes
Attached to Project— M5 Bugs
Opened by Ali Saidi (saidi) - Wednesday, 09 May 2007, 05:02PM
Last edited by Ali Saidi (saidi) - Friday, 11 April 2008, 02:04PM
Opened by Ali Saidi (saidi) - Wednesday, 09 May 2007, 05:02PM
Last edited by Ali Saidi (saidi) - Friday, 11 April 2008, 02:04PM
| Bug | |
| Memory System | |
| New | |
| Ali Saidi | |
| All |
| High | |
| Normal | |
| 1.1 | |
| 2.0 | |
| Undecided | |
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Right now the bus bridge is doing a functional read when it sees a partial block write. It should really be using a 1 line cache to do it's work for it, but the caches probably need to be in a better state before this happens.
This works now, however the implementation is non-ideal. We need more control over the latency on both sides of the cache. Generally, memory side requests should be handled quickly, while device side requests might take longer. However unless we stick another bus bridge between the devices and the cache this isn't really configurable.
This works now, however the implementation is non-ideal. We need more control over the latency on both sides of the cache. Generally, memory side requests should be handled quickly, while device side requests might take longer. However unless we stick another bus bridge between the devices and the cache this isn't really configurable.
This task blocks these from closing
Here is a diagram of possible bus bridge diode connection.
Works, but cache needs to send out write invalidates instead of readex, writebacks on full block writes and maybe eagerly writeback partial blocks
Another problem with this is that there is that I believe the hit latency governs how fast the cache can respond to snoops that require a block transfer. This is annoying because presumably an I/O cache would have a fast memory side interface and a slower device side interface (the reverse of a normal cache). Getting latencies from i/o devices right is harder in this case. We probably want a separate snoop response latency and hit latency in the caches