FS#207 — Add ability for O3CPU to be used without caches
Attached to Project— M5 Bugs
Opened by Kevin Lim (ktlim) - Thursday, 30 November 2006, 01:48PM
Last edited by Ali Saidi (saidi) - Friday, 11 April 2008, 02:26PM
Opened by Kevin Lim (ktlim) - Thursday, 30 November 2006, 01:48PM
Last edited by Ali Saidi (saidi) - Friday, 11 April 2008, 02:26PM
| Bug | |
| CPU | |
| New | |
| Kevin Lim | |
| All |
| Low | |
| Normal | |
| 1.1 | |
| 2.1 | |
| Undecided | |
 |
Currently the O3CPU has to be used with caches. The issue is that the O3CPU, like the 21264, will squash and refetch a load and all younger instructions if the cache responds that it is currently busy. This naturally limits the rate of access of the Dcache. However, when hooked up directly to a bus, both the fetch and LSQ share the bus, and because fetch is tick()'d before the IEW stage, fetch gets priority to access the bus. This can result in an infinite loop where a load needs to access the bus, but can't because fetch has already used the bus, and is squashed and refetched.
The solution is to allow the O3CPU to have a replay list that will replay all loads that tried to access the bus but couldn't. Because the CPU doesn't issue the dependents of the loads until after the load completes, there won't be an issue with dependents having to be replayed.
I have this code written but not integrated well. I'd like to update the O3CPU to have a parameter that selects which behavior occurs on a load access failing.
The solution is to allow the O3CPU to have a replay list that will replay all loads that tried to access the bus but couldn't. Because the CPU doesn't issue the dependents of the loads until after the load completes, there won't be an issue with dependents having to be replayed.
I have this code written but not integrated well. I'd like to update the O3CPU to have a parameter that selects which behavior occurs on a load access failing.