M5 Bugs

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ID Task Type Severity Summary Status Due In Version Progress
13 Minor Enhancement Low make non-full-system use TLBs, flat memory Assigned 2.1 80% complete
42 Minor Enhancement Low Dump stack trace on sigsegv Assigned 0% complete
48 Minor Enhancement Low measure benefit of detecting correct path early Unconfirmed 0% complete
50 Minor Enhancement Low Update statistics to use new models more efficiently Waiting on Customer 0% complete
52 Bug Low Get rid of -Wno-sign-compare Unconfirmed 0% complete
73 Minor Enhancement Low Snoop for hits in the write/victim buffer Unconfirmed 0% complete
77 Minor Enhancement Low Add support for inclusion/exclusion Unconfirmed 0% complete
151 Minor Enhancement Low Make adding children an explicit operation in Python config New 0% complete
152 Minor Enhancement Low Test/flesh out VectorPort connections New 0% complete
161 Minor Enhancement Low Should warn (or maybe error) when re-parenting children New 0% complete
174 Validation Low Test DRAM model New 2.1 0% complete
176 Minor Enhancement Low add per-SimObject trace enable flags New 0% complete
180 Bug Low Fix byte swapping New 2.1 0% complete
182 Minor Enhancement Low refactor Fault object classes New 0% complete
196 Minor Enhancement Low Make Checker handle multiple threads New 0% complete
205 Bug Low Build doesn't work if path contains spaces Unconfirmed 0% complete
207 Bug Low Add ability for O3CPU to be used without caches New 2.1 70% complete
209 Bug Low Implement Sparc memory syncronization instructions Assigned 2.1 0% complete
210 Minor Enhancement Low MP SPARC booting New 2.1 0% complete
211 Minor Enhancement Low Generate SPARC HV and MD config blobs from python config New 2.1 0% complete
Showing tasks 41 - 60 of 101Page 3 of 6   --   < Previous - 1 - 2 - 3 - 4 - 5 - 6 - Next >