M5 Bugs
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M5 Bugs
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2.0 release
2.1
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Ali Saidi
Gabe Black
Kevin Lim
Korey Sewell
Lisa Hsu
Nathan Binkert
Ron Dreslinski
Steve Reinhardt
Andrew Schultz
Erik Hallnor
Jenny Treichler
Steve Raasch
Nathan Binkert
Gabe Black
Lisa Hsu
Korey Sewell
Kevin Lim
Ron Dreslinski
Ali Saidi
Steve Reinhardt
test
James
Vilas Sridharan
Sasa Tomic
Jonas Diemer
Miles Kaufmann
Richard
vincent
Meng, Ke
Matthew Horsnell
Clint Smullen
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ID
Task Type
Severity
Summary
Status
Due In Version
Progress
91
Minor Enhancement
Medium
Add DPRINTFs for trace addr and marked requests
Unconfirmed
2.1
134
Bug
Medium
jobs scripts fail if no groups aren't required for a checkpoint
Unconfirmed
190
Minor Enhancement
Medium
Get Ozone CPU working
New
2.1
192
Bug
Medium
Fix makeExtMI to be more flexible with ISAs
New
204
Bug
Medium
Consistent Schedule Later Call
New
2.1
257
Bug
Medium
pkt->finishTime and pkt->firstWordTime aren't used consistantly
New
2.0
262
Bug
Medium
Make default parameters more reasonable
New
2.1
267
Bug
Medium
Bus needs to handle responses even when bus is blocked for requests
New
2.0
268
Minor Enhancement
Medium
O3 LSQ needs coherence support
New
2.1
270
Bug
Medium
cache and bus reschedule on next tick instead of next clock
New
2.0
289
Bug
Medium
actual cache latency is higher than set one
Unconfirmed
308
Bug
Medium
SCons compatibility problems
Assigned
310
Validation
Medium
Add checkpoint/restore/switch tests to regressions
New
2.1
311
Minor Enhancement
Medium
Integrated one of the many other DRAM models that have bene written for M5
New
317
Bug
Medium
Dynamic thread creation in O3 is broken
New
328
Bug
Medium
Bitfield definitions in ARM ISA
New
2.1
330
Bug
Medium
Regressions no longer retry on user kill
New
331
Bug
Medium
Process output files don't obey -d flag
New
332
Bug
Medium
minor FS checkpoint/restore discrepancies
New
3
Bug
Low
error on running past end of EIO trace
New
Showing tasks 21 - 40 of 101
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