File list
This special page shows all uploaded files. When filtered by user, only files where that user uploaded the most recent version of the file are shown.
 Date |
Name | Thumbnail | Size | User | Description | Versions |
|---|---|---|---|---|---|---|
| 08:10, 24 April 2012 | Bus.png (file) |  | 22 KB | Wilwan01 | (Traffic in the Bus.) | 2 |
| 10:07, 16 March 2012 | TimingSimpleCPU.jpg (file) |  | 131 KB | Mat2909 | 1 | |
| 10:02, 16 March 2012 | AtomicSimpleCPU.jpg (file) |  | 71 KB | Mat2909 | (AtomicSimpleCPU) | 1 |
| 13:42, 14 February 2012 | Gem5 initialization call sequence.png (file) |  | 58 KB | Plafratt | (Figure showing function call sequence during the initialization of gem5.) | 1 |
| 13:40, 24 November 2011 | Bbench results.png (file) |  | 132 KB | Atgutier | 1 | |
| 13:39, 24 November 2011 | Bbench home.png (file) |  | 117 KB | Atgutier | 1 | |
| 11:08, 16 July 2011 | O3pipeview.png (file) |  | 75 KB | Saidi | 1 | |
| 10:33, 3 April 2011 | MOESI CMP directory L2cache FSM part 2.jpg (file) |  | 200 KB | Rsen | (FSM (part 2) of the L2 cache controller for the MOESI_CMP_directory cache coherence protocol.) | 1 |
| 07:21, 3 April 2011 | MOESI CMP directory L2cache FSM part 1.jpg (file) |  | 333 KB | Rsen | (moved position of the {ILOS -> OLS} transition annotation.) | 3 |
| 09:24, 1 April 2011 | Interconnection network.jpg (file) |  | 38 KB | Tushar | (Interconnection Network High-Level figure) | 1 |
| 09:23, 1 April 2011 | Garnet router.jpg (file) |  | 47 KB | Tushar | (Router Microarchitecture and Pipeline modeled in Garnet.) | 1 |
| 09:22, 1 April 2011 | Simple network.jpg (file) |  | 12 KB | Tushar | (Simple Network Figure from GEMS ISCA tutorial) | 1 |
| 22:00, 31 March 2011 | MOESI hammer dir FSM.jpg (file) |  | 46 KB | Somayeh | 1 | |
| 18:16, 31 March 2011 | Mc addr command timing back to back.jpg (file) |  | 52 KB | Rsen | (Timing diagram for back-to-back command and address sequences for the Memory Controller. The figure was created by Andy Phelps in 2008.) | 1 |
| 17:12, 31 March 2011 | Mc addr command timing.jpg (file) |  | 45 KB | Rsen | (Timing diagram of address and command signals for the Memory controller. This figure was created by Andy Phelps in 2008.) | 1 |
| 16:36, 31 March 2011 | Mc data struct.jpg (file) |  | 79 KB | Rsen | (High level view of memory controller data structures. Adapted from a figure created by Andy Phelps in 2008.) | 1 |
| 21:00, 30 March 2011 | MOESI hammer cache FSM.jpg (file) |  | 62 KB | Somayeh | 1 | |
| 06:41, 27 March 2011 | MOESI CMP directory L1cache optim FSM.jpg (file) |  | 90 KB | Rsen | (FSM for L1 cache controller optimizations (SM, OM states) for MOESI_CMP_directory coherence protocol.) | 1 |
| 04:51, 27 March 2011 | MOESI CMP directory L1cache FSM.jpg (file) |  | 207 KB | Rsen | (FSM for L1 cache controller for MOESI_CMP_directory coherence protocol.) | 1 |
| 20:36, 26 March 2011 | MOESI CMP directory dir FSM.jpg (file) |  | 152 KB | Rsen | (Corrected transitions from I on GETS.) | 2 |
| 18:28, 26 March 2011 | MI example dir FSM.jpg (file) |  | 113 KB | Rsen | (updated FSM to include transition on PUTX.) | 2 |
| 19:08, 25 March 2011 | MI example cache FSM.jpg (file) |  | 97 KB | Rsen | (FSM for the cache controller for MI_example coherence protocol.) | 1 |
| 03:32, 25 March 2011 | Mc overview.jpg (file) |  | 159 KB | Rsen | (High level overview of Memory Controller and memory organization.) | 1 |
| 17:28, 24 March 2011 | Slicc overview.jpg (file) |  | 116 KB | Rsen | (Added a FSM picture for the state machine. Both components of the picture appear in the GEMS tutorial in ISCA 2005.) | 2 |
| 18:50, 21 March 2011 | Topology overview.jpg (file) |  | 168 KB | Rsen | (High-level picture of various well-known topologies. Individual components were taken from the GEMS tutorial in ISCA 2005.) | 1 |
| 12:42, 19 March 2011 | Ruby overview.jpg (file) |  | 96 KB | Rsen | (Reverted to version as of 19:36, 19 March 2011) | 4 |
| 19:24, 17 March 2011 | Example.jpg (file) |  | 2 KB | Saidi | (test) | 1 |
